1. Field of the Invention
The present invention relates to a method of making a memory cell of a semiconductor memory device, and more particularly to a method of making a memory cell of a semiconductor memory device such as a DRAM.
2. Description of the Related Art
In a DRAM which is one of typical memory integrated circuits, each memory cell is constituted of a MOS transistor and a capacity element (capacitor), and information is written in or read out of the memory cell by storing or detecting electric charges in the capacitor through switching operation of the MOS transistor.
As a capacitor of the DRAM memory cell, a stacked capacitor in which a conductive thin film (a cell plate) of a second layer is laminated on a conductive thin film (a storage node) of a first layer is widely used.
An example of a conventional DRAM memory cell using the stacked capacitor cell is shown in FIG. 3.
As shown in FIG. 3, a gate oxide film 102 and a gate electrode 103 are formed on a silicon substrate 101. Source and drain regions 104 are formed in the silicon substrate 101 in self-alignment manner with respect to the gate electrode 103. Thus, the MOS transistor as an access transistor is formed of the gate electrode 103 and the source and drain regions 104.
A storage node (a lower electrode) 112 is connected to a source or drain region 104 through a contact hole 106 formed in an interlayer insulator 105. Further, a reference numeral 113 represents a capacitor insulator, and 114 represents a cell plate (an upper electrode). A capacitor is formed of the upper electrode 114, capacitor insulator 113 and lower electrode 112. The memory cell is constituted of the access transistor described above and the capacitor.
As a semiconductor memory device is more highly integrated in recent years, the number of elements in one chip is increased and the space for each capacitor is reduced.
Accordingly, in a DRAM memory cell having a stacked capacitor structure described above, the capacitance of the capacitor is no longer sufficient with the reduction of the space for the capacitor and it is difficult to ensure sufficient reliability in reading and writing information stably out of and in the memory cell in a highly integrated circuit element having a memory capacity of 64M bits or more for instance.
Accordingly, in order to increase the capacitance of a capacitor having a limited space, a method is proposed to form a plurality of fine projections on an upper surface of a lower electrode of a capacitor so as to increase the effective electrode area, thereby to increase the capacity of the capacitor as described in IEDM (1990) pp 659.about.662.
According to this method, in the process of depositing a polycrystalline silicon thin film which provides the lower electrode on a semiconductor substrate by a CVD method, an amorphous silicon thin film is deposited while controlling temperature and pressure for forming the thin film, thereby to form a plurality of fine projections on the upper surface of this thin film.
However, this method involves problems such that, when the lower electrode of a stacked capacitor is formed using the method described above, it is necessary to repeat deposition several times in order to obtain a thin film having a desired thickness, since the fine projections on the upper surface of the thin film is reduced when the desired thickness of 0.2 .mu.m of the thin film is formed by deposition in one time, or precise temperature control is required with allowance of .+-.5.degree. C. or less since the size of the fine projection depends delicately on the temperature at which the thin film is formed. Thus, the control of a process of forming a thin film is complicated.